ALP035 Technology

Features:

  • LV nMOS & pMOS transistors (3.3V)
  • HV nMOS & pMOS transistors (12V)
  • Special transistors (ie. 0Vt native or pFET with N+ poly available upon request, needing no additional masks)
  • Schottky diodes, Poly diodes
  • Double poly capacitors
  • High resistance poly, Poly laser fuses
  • PBLOCOS isolation
  • Retrograde wells
  • Two gate oxides (LV, HV)
  • Two Poly layers (EEPROM cell and capacitors)
  • ONO for inter-poly dielectric
  • Salicided gate poly and Source/Drain
  • Barrier and W plugs
  • Three Metal levels (AlCu)
  • CMP planarisation
  • Digital library has density around 20kgates/mm2

- EEPROM -

  • Cell structure : 2 transistors cells
  • Programming modes (write/erase): very low power FN/FN allowing parallel bit programming
  • Write speed/bit: 8μs if 256bit word
  • Programming current/cell < 10 nA
  • Retention: 10 years
  • Endurance: guaranty 100kcycles, typical > 1Mio cyclesConductors: Copper

Technology:

The EM ALP035D Mixed Signal technology is designed for low-power, low-voltage applications which need high performance EEPROM memory. Use of adapted threshold voltages, optimized stand-by currents and Fowler-Nordheim programming for the EEPROM make this process particularly suitable for battery-operated or RF-powered circuits.

Additionally, the integration density reached with the 0.35μm design rules, when combined with low process complexity, provides cost effective manufacturing. This is supported by well characterized devices and highly reliable double poly capacitors providing the key to precision analog products.

Overall ALP035 is optimized for a large variety of consumer, industrial, communication and automotive products.

Development:

The developments are realized completely inside HMT’s design center. ALP035Based on a close relationship between the customer, the foundry and the development engineer, the development covers all items of concept analysis, pre-study, project definition, design and industrialization each under the responsibility of HMT microelectronic. For every product, a specific test program and DUT-board are developed and, according to the requirement and application, appropriate qualification procedures are carried out.

Production:

The wafer production, wafer test, packaging, final test, conditioning and delivery of ASIC’s is done under the full responsibility of HMT microelectronic.

Packaging:

A wide range of packages are available: SO, SSOP, TSSOP, PLCC, Flat-Pack, DIL, BGA, TBGA, MLP, FCOL, Die-Form, CSP, studbump (flip-chip), COB