C05A Technology

Features:

  • Analog cells:
    - Bandgaps
    - Comparators
    - Operational amplifiers
    - Transconductance amplifier
    - Oscillators (e.g. Crystal, RC)
    - Class AB amplifiers
    - Bias circuitry
    - Switched capacitor filter compiler
    - High ohmic polysilicon resistors (1kΩ/sq)
    - High value double poly capacitors (1.1 nF/mm2)
  • Digital Library:
    - Double Layer Metal: 5000 gates/mm2
    - Over 430 core and I/O cells
    - High current output cells (24mA sink, 12mA source)
    - Slew rate control and current spike supression
    - 5V tolerant I/O cell
    - Active pull up and down devices
    - Buskeeper I/O functions
    - Single port, dual port RAM, ROM, FIFO and multiplier compilers
    - OTP poly zapping cells
  • Operational Power Supply:
    - 2.7 to 3.6V digital
    - 1.0 to 3.6V analog
  • IP Cores:
    - μController (e.g. 8051, 8308, 6502, ARM7TDMI)
    - AD and DA Converter (up to 16 Bit delta-sigma Converter, approximate successive 8-bit rail to rail)
    - LCD driver
    - PLL up to 18 MHz input clock frequency range
    - Low Drop Voltage Regulator
    - Shunt Regulator
    - Low Offset Chopper Amplifier
    - Codec
    - ISDN-Interface (S- and U, Line driver)
    - Integrated, tunable continuous time filter
  • Design for Testability:
    - JTAG Boundry Scan
    - Edge Level Sensitive Design Scan
    - Automatic Test Pattern Generator based on LSSD Latch

 

Technology:

CMOS 0.5μ, triple layer metal mixed signal process, featuring self-aligned twin tub N and P wells, policide or polysilicon gates to achieve sub-nanosecond internal speeds, offering low power dissipation and high noise margin.

Development:

The developments are realized completely inside HMT’s design center. Based on a close relationship between the customer, the production plant and the development engineer, the development covers C05Aall items of concept analysis, pre-study, project definition, design and industrialization under the responsibility of HMT microelectronic Ltd. For each  product, a specific test program and DUT-board is developed and depending on request and application, an appropriated qualification procedure is run.

Production:

The wafer production, wafer test, packaging, final test, conditioning and delivery of such developed ASIC’s is done under the full responsibility of HMT microelectronic Ltd.

Packaging:

Various package are available: SO, SSOP, TSSOP, PLCC,  Flat-Pack, DIL, BGA, TBGA, Die-Form