C07A Technology

Features:

  • Analog cells:
    - Bandgaps
    - Comparators
    - Operational Amplifiers
    - Transconductance Amplifier
    - Oscillators (e.g. Crystal, RC)
    - Class AB Amplifiers
    - Bias Circuitry- Switched Capacitor Filter Compiler
  •  Digital Core Library:
    - Double Layer Metal: 1750 gates/mm2
    - Over 120 core cells
    - Over 100 I/O cells
    - High current Output cells (24mA sink, 12mA source)
    - Dual supply voltage possibility (e.g. core 3.3V,
      periphery 5V)
    - Single port, dual port RAM, ROM, FIFO and
      multiplier Compilers
    - OTP poly zapping cells: 90Bit/mm2
  • Operational Power Supply:
    - 4.5 to 5.5V digital
    - 2.7 to 3.6V digital
    - 2.7 to 5.5V analog
  • IP Cores:
    - μController (e.g. 8051, 8308, 6502)
    - AD and DA Converter (up to 16 Bit delta-sigma
      Converter, approximate successive 8-bit rail to rail)
    - LCD driver
    - PLL up to 192 MHz input range
    - Low Drop Voltage Regulator
    - Shunt Regulator
    - Low Offset Chopper Amplifier
  • Option:
    - E2PROM:4kBit/mm2, 220 ns read cycle
    - Triple Layer Metal: 3500 gates/mm2
  • Design for Testability:
    - JTAG Boundry Scan
    - Edge Level Sensitive Design Scan
    - Automatic Test Pattern Generator based on LSSD
      Latch

Technology:

CMOS 0.7μ, double or triple layer metal mixed signal process, featuring self-aligned twin tub N and
P wells, policide or polysilicon gates to achieve sub-nanosecond internal speeds, offering low power
dissipation and high noise margin.

Development:

The developments are realized completely inside HMT’s design center. Based on a close
relationship between the customer, the production plant and the development engineer, the
development covers all items of concept analysis, pre-study, project definition, design and
industrialization under the responsibility of HMT microelectronic Ltd. For each product, a specific test
program and DUT-board is developed and
depending on request and application, an
appropriated qualification procedure is run.

Production:

The wafer production, wafer test, packaging,
final test, conditioning and delivery of such
developed ASIC’s is done under the full
responsibility of HMT microelectronic Ltd.

Packaging:

Various package are available: SO, SSOP,
TSSOP, PLCC, Flat-Pack, DIL, BGA, TBGA, Die-Form