SCMOS3EE Technology

Features:

  • Standard Devices:
    - CMOS Transistors (±5.5V)
    - Diode (antifuse)
    - Bipolar Transistors (50V vertical PNP)
    - Resistors (diffused: 1kΩ/􀂆; poly:45Ω/􀂆)
  • Optional Devices:
    - CMOS Transistors (±16V; ±24V)
    - Diodes (7V zener; schottky)
    - Capacitors (poly-poly; sandwich; varactor)
    - Resistors (hipo: 1kΩ/􀂆 or 10kΩ/􀂆)
    - EEPROM cells (single polysilicon cell, 1.8V to
      5V power supply)
  • Digital Library:
    - 37 core cells
  • Operational Power Supply:
    - Standard: up to 5V
    - High-voltage devices: up to 24V
  • Typical Applications:
    - Electronic Tag
    - Contactless Product
    - Codec
    - Interfaces

 

Technology:

The SCMOS3EE is a 0.5μm digital and mixed-signal CMOS twin-well technology with 2 or 3 metal layers. Different optional functions (including analog devices, high-voltage devices and EEPROM memory blocks), allow the adaptation of the process to specific customer requirements.

Development:

The developments are realized completely inside HMT’s design center. Based on a close relationship between the customer, the production plant and the development engineer, the development covers all items of concept
analysis, pre-study, project definition, design and industrialization under the responsibility of HMT microelectronic Ltd. For each product, a specific test program and DUT-board is developed and depending on requirement and application, an appropriate qualification procedure is undertaken.

Production:

The wafer production, wafer test, packaging, final test, conditioning and delivery of ASIC’s is done under the full responsibility of HMT microelectronic Ltd.

Packaging:

Various package are available: SO, SSOP, TSSOP, PLCC, Flat-Pack, DIL, BGA, TBGA, MLP, Die-Form.