XDH10 Technology

Main XDH10 Features:                                          Process Features:

  • Pre-defined 650V and 350V n-channel DMOS
    transistors with different resistances
  • Pre-defined bipolar transistors for different voltages
  • Pre-defined HV PMOS for different voltages
  • Diodes
  • Poly Silicon resistors (n+, low TC, high value)
  • Poly-Poly capacitor
  • 650V sandwich capacitor
  • Dielectric Insulation with trench insulated SOI wafers
  • N+ buried layer contacted via n+ sinker
  • Double diffused self aligned DMOS process
  • Double gate process for DMOS and CMOS
  • Double or triple layer poly-silicon
  • High resistance and/or low TC poly silicon optional
  • Triple layer metal is power metal
  • PSG passivation reinforced with Polyimide
  • 1.0μm Design Rules
  • Thick SOI wafer with 6’’ diameter
  • CMOS devices compatible with XC10 process

Technology:

XDH10 is a dielectric trench insulated smart power technology. The main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL/piezo driver ICs for applications using
220 V net supply. The typical breakdown voltage of the HV-DMOS devices is >350 V or >650 V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to
provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bidirectional high voltage trench insulation on the same die. The 14 layer core process module is available for 650 V breakdown voltage of the HVDMOS. This process module provides trench insulation, single level poly with thick gate oxide, and a third level metal with power metal.

Development:

The developments are realized completely inside HMT’s design center. Based on a close relationship between the customer, the foundry and the development engineer, the development covers all items of concept
analysis, pre-study, project definition, design and industrialization each under the responsibility of HMT microelectronic. For every product, a specific test program and DUT-board are developed and, according to
the requirement and application, appropriate qualification procedures are carried out.

Production:

The wafer production, wafer test, packaging, final test, conditioning and delivery of ASIC’s is done under the full responsibility of HMT microelectronic.

Packaging:

A wide range of packages are available: SO, SSOP, TSSOP, PLCC, Flat-Pack, DIL, BGA, TBGA, MLP, FCOL, Die-Form, CSP, studbump (flip-chip), COB