HMT7748 GENIE IO-Link DEVICE DUAL PHY
The GENIE IO-Link DEVICE DUAL PHY is a transceiver between a microcontroller with a sensor or actuator function and a 24V power and signalling cable, specified to support IO-Link.
- Integrated UART peripheral with M-sequence handling (inc. checksum) for all IO-Link sequences to specification 1.1, up to a data buffer size of 15 octets
- Single byte UART mode for unlimited M-sequence size and continuous data transfer
- Transparent UART mode for special applications
- Quartz free IO-Link clock extraction and timing generation at 38.4kBaud and 230.4kBaud
- Dual outputs independently configured to be high-side, low-side or push-pull (<10Ω)
- Configurable output doubling for additional drive strength requirements (nom. 400mA)
- Fast switching time (<1μs)
- Configurable short circuit current limit and reporting
- Zener limits for rapid inductive load switch off
- 5V to 35V supply range
- 5V and 3.3V, 50mA linear regulators
- Configurable frequency & voltage (5V-9V), 50mA DC-DC regulator
- Software controlled DC-DC sleep mode
- Internal reverse polarisation diode (DOUT pin)
- Full zero current reverse polarity protection
- Over-voltage protection to 35V
- Configurable under-voltage detection
- ESD protection to 4kV
- EMC surge protection to IEC 60255-5 (2A/50μs)
- Configurable thermal shutdown levels
- 7-bit, calibrated, temperature measurement
- Two current mode LED outputs
- small format 4mm x 4mm, 20LD QFN package
At start-up, power is applied via the cable on VPLUS and the device is powered with a 3.3V or 5V supply from the linear and dc-dc regulators. On leaving reset the microcontroller proceeds to configure the DUAL PHY to the desired operating mode.
The DIO pin is a fully protected I/O which can be driven or sampled independently via SPI. With external connection to CQ, it may also be used to provide a single output with doubled drive strength.
In operation, the device is run in IO-Link mode where data is transferred with UART frames, or in SIO mode where CQ is driven according to the sensor state.
If the DUAL PHY is placed in listen mode, or receives a wake-up request from the IO-Link master, then the DUAL PHY waits for a UART M-sequence on the CQ line. If one is received, its checksum and parity are checked by the DUAL PHY, and a interrupt is generated on INT.
The microcontroller now reads the incoming M-sequence, and composes a return sequence via the SPI. The DUAL PHY adds parity and checksum and transmits the frame on the CQ line, using a clock trimmed to the master clock.
Development and demonstration modules
Please see GENIE Explorer II on our website.
|15.20130||HMT7748 IO-Link Device Dual PHY||<10||samples free of charge|
|15.20130||HMT7748 IO-Link Device Dual PHY||10...40||request quotation|
Delivery terms: FCA Biel, Switzerland
HMT7748 samples are available in QFN 20LD 4x4mm